Field effect transistors are devices commonly used in the fabrication of integrated circuitry. Such devices conventionally comprise a pair of conductive source/drain regions having a semiconductive channel region therebetween. A conductive gate is received operably proximate the channel region, and is separated therefrom by a dielectric material. Application of suitable voltage to the gate causes current to flow from one of the source/drain regions to the other through the channel region, accordingly operating as a switch depending upon voltage application to the gate.
Integrated circuitry fabrication technology continues to strive to make smaller and denser circuits, with the corresponding size of individual devices, of course, shrinking in the process. As the size of field effect transistors gets smaller and the length of the channels between the source/drain regions shortens, complex channel profiles have been developed to achieve desired “on” threshold voltages and to alleviate undesired short channel effects. Such profiles for the channel regions can include gating the channel region from multiple sides. One example such device is a FinFET. Such structures are built on semiconductor-on-insulator substrates in which the semiconductor material (typically silicon) is etched into a “fin”-like shaped channel body of the transistor, with the conductive gate wrapping up and over the “fin”.
“Fin”-shaped channel body regions have also been proposed in bulk semiconductor processing in addition to semiconductor-on-insulator processing. Etching of the semiconductor material to produce the typical vertically-extending channel fins can create shoulder areas of semiconductor material adjacent the base of the fins. Such areas can result in undesired parasitic capacitance as the conductive gate is also typically received over these shoulder semiconductor material areas.